1. Field of the Invention
This invention relates to processors and, more particularly, to implementation of cache memory systems.
2. Description of the Related Art
To improve execution performance, processors may include one or more levels of cache memories (commonly referred to as “caches”). A cache may be used to store frequently accessed instructions and/or memory data, and improve performance by reducing the time for the processor to retrieve these instructions and data. A processor may include a fast first-level (L1) cache backed by a larger, slower second-level (L2) cache. Some processors may include a third-level (L3) cache for further performance improvement.
In some multicore processors and some single-core processors with multiple bus masters, the L2 and/or L3 caches may be shared. This sharing requires coherency mechanisms to ensure that cached memory being accessed by one cache user has not been modified by another cache user. In various computing systems, different coherency protocols, such as, e,g, Modified-Owned-Exclusive-Shared-Invalid (MOESI), Modified-Exclusive-Shared-Invalid (MESI), or any other suitable coherency protocol, may be employed.
An entry in a cache may be referred to as a cache line. Each cache line in a cache may include the data being stored, flags corresponding to the coherency state, and an address tag. A cache tag may include all or a part of the original address of the data being stored in the cache line, an index indicating in which cache line the cached data is stored, and an offset indicating where in each cache line the specific data is located. A processor may access a cache with a direct address of the memory location, a translated address based on lookup tables, or through an address calculated based on an instruction's address mode.
Instruction Set Architectures (ISAs) may include multiple addressing modes. One common addressing mode is a relative offset mode. In a relative offset mode, the address is calculated by adding a signed number to the current program address (referred to in various embodiments as program counter, instruction pointer, instruction address register or instruction counter). An instruction with this type of addressing mode may require the processor to utilize clock cycles to calculate the address every time the instruction is executed.